Generally, among nonvolatile memory devices capable of electrically programming and erasing data, flash memory devices are increasingly highlighted as a data storage device because the cell array used therein has a generally high degree of integration.
As memory devices today are generally highly integrated, a channel length and width of a cell transistor may be reduced. A memory device may also have a structure capable of obtaining relatively high cell current despite a low operational voltage, which may suppress a short channel effect, and may suppress a program disturbance between memory cells.
FIG. 1 is an equivalent circuit diagram illustrating a portion of a conventional NAND type memory device, and FIG. 2 is a plane view illustrating a portion of the conventional NAND type memory device.
Referring to FIG. 1, a conventional NAND type flash memory device, which is a representative flash memory device, includes a cell array provided with a plurality of cell strings. Each of the cell strings is configured with a ground select transistor, a string select transistor, and a plurality of memory cells. The ground select transistor and the string select transistor are connected in series between a source region and a drain region. The plurality of memory cells are connected in series between the ground select transistor and the string select transistor. The cell array includes a plurality of ground and string select gate lines GSL and SSL, and a plurality of word lines WLn disposed between the string select gate line SSL and the ground select gate line GSL. A bit line BLn is arranged such that it crosses over the word line WLn and is connected to the drain region through a bit line contact DC. The source regions are interconnected to each other in a column direction to thereby form a common source line CSL.
The ground select gate line GSL, the string select gate line SSL, and the word line WLn are arranged such that they cross over active regions ACT defined by a device isolation layer ISO. The common source line CSL is arranged such that it crosses over the active region between the ground select gate lines GSL of an adjacent cell string and is electrically connected to the underlying active regions. The bit line contact DC is in contact with the active region between the adjacent string select lines SSL and is connected to the bit line (not shown) crossing over the word lines.
A nonvolatile memory device may have a fin field effect transistor (FinFET) structure. The FinFET structure, which uses a sidewall of a fin-shaped active region as a channel of a transistor, may include beneficial features, such as low sub-threshold swing, high transconductance, suppression of short channel effect, and the like. Therefore, the FinFET may be considered an adaptive structure for securing characteristics of the transistor of which the feature size is 50 nm or less. Because the FinFET structure has certain advantages, such as high controllability of a gate with respect to a channel, low depletion capacitance, and so forth, the FinFET structure may be used in various nonvolatile memory devices, such as a flash memory device.